Minimizing leakage energy with modulo scheduling for VLIW DSP processors

IFIP International Federation for Information Processing

Volumn 271, Issue , 2008, Pages 111-120

  Wang, Meng ^a   Shao, Zili ^a   Liu, Hui ^b   Xue, Chun Jason ^c  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

^b XIDIAN UNIVERSITY   (China)

^c CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; ENERGY CONSERVATION; MIDDLEWARE; SCHEDULING;

DSP APPLICATION; DSP PROCESSOR; FUNCTION UNIT; LEAKAGE ENERGIES; MANAGEMENT SCHEME; MODULO SCHEDULING; TECHNOLOGY SCALING; TOTAL POWER CONSUMPTION;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 47249142497     PISSN: 15715736     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-0-387-09661-2_11     Document Type: Conference Paper

References (11)

1. The Trimaran Compiler Research Infrastructure. http://www.trimaran.org/.
2. B.R.Rau. Iterative modulo scheduling: An algorithm for software pipeling loops. In 27th Annual International Symposium on Microarchitecture pages 63-74.
3. J. Butts and G. Sohi. A static power model for architects. In Proceedings of The 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pages 191-201, 2000.
4. D. Sylvester and H.Kaul. Power-driven challenges in nanometer design. IEEE Design and Test of Computers, 18:12-22, 2001.
5. H.S.Kim, N.Vijakrishnan, M.Kandemir, and M.J.Irwin. Adapting instruction level parallelism for optimizing leakage in vliw architectures. In ACM SIFPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, pages 275-283.
6. W. Liao, J. M.Basile, and L. He. Leakage power modeling and reduction with data retention. In 2002 IEEE/ACM International Conference on Computer-Aided Design, pages 714-719, 2002.
7. M.R.Guthaus, J.S.Ringenberg, D.Ernst, T.M.Austin, T.Mudge, and R.B.Brown. Mibench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE International Workshop on Workload Characterization, pages 3-14, 2001.
8. R.Nagpal and Y.N.Srikant. Compiler-assisted leakage energy optimization for clustered vliw architectures. In 6th ACM/IEEE International Conference on Embedded Software, pages 233-241, 2006.
9. S.Dropsho, V.Kursun, D.H.Albonesi, S.Dwarkadas, and E.G.Friedman. Managing static leakage energy in micro-processor functional units. In the 35th annual ACM/IEEE international symposium on Microarchitecture pages 321-332.
10. T.N.Mudge. Power: A first class design constraint for future architecture and automation. In the 7th International Conference on High Performance Computing, pages 215-224.
11. V. Zivojnovic, J.Martinez, C.Schlager, and H.Meyr. Dspstone: A dsp-oriented benchmarking methodology. In Proceedings of the 1994 International Conference on Signal Processing Applications and Technology, 1994.