Highly scalable phase change memory with CVD GeSbTe for sub 50nm generation

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 102-103

  Lee, J I ^a   Park, H ^a   Cho, S L ^a   Park, Y L ^a   Bae, B J ^a   Park, J H ^a   Park, J S ^a   An, H G ^a   Bae, J S ^a   Ahn, D H ^a   Kim, Y T ^b   Horii, H ^a   Song, S A ^c   Shin, J C ^a   Park, S O ^a   Kim, H S ^a   Chung, U In ^a   Moon, J T ^a   Ryu, B I ^a  

^a Process Development Team   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

CMP; Confined; CVD; GST; PRAM device

Indexed keywords

ANTIMONY ALLOYS; ASPECT RATIO; GERMANIUM; PHASE CHANGE MEMORY; PHOTORESISTS; SYSTEM THEORY;

HIGH ASPECT RATIO (HAR); PHASE CHANGES; RESET CURRENTS; SUB-50 NM; VLSI TECHNOLOGIES;

CHEMICAL VAPOR DEPOSITION;

EID: 47249140759     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339744     Document Type: Conference Paper

References (4)

1. Y.N. Hwang et al., IEDM Tech. Dig., p. 37.1.1, 2003.
2. S.L. Cho et al., Sump. VLSI Tech dig., p. 96, 2005.
3. S.J. Ahn et al., Sump. VLSI Tech dig., p. 98, 2005.
4. A.L. Lacaita., IMST EPCOS., 2006.