Improved cell performance for sub-50 nm DRAM with manufacturable bulk FinFET structure

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 164-165

  Lee, Deok Hyung ^a   Lee, Sun Ghil ^a   Yoo, Jong Ryeol ^a   Buh, Gyoung Ho ^a   Yon, Guk Hyon ^a   Shin, Dong Woon ^a   Lee, Dong Kyu ^a   Byun, Hyun Sook ^a   Jung, In Soo ^a   Park, Tai Su ^a   Shin, Yu Gyun ^a   Choi, Siyoung ^a   Chung, U In ^a   Moon, Joo Tae ^a   Ryu, Byung Il ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; LEAKAGE CURRENTS;

BULK FINFET; CELL PERFORMANCES; DRAM CELL TRANSISTORS; FRONT END OF LINE (FEOL) PROCESSING; NOVEL CONCEPT; OFF STATE LEAKAGE CURRENT; OFF-STATE LEAKAGE; SATURATION CURRENTS; SHORT CHANNELS; SUB-50 NM; VLSI TECHNOLOGIES;

FIELD EFFECT TRANSISTORS;

EID: 47249132836     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339767     Document Type: Conference Paper

References (6)

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3. Sung-Woong Chung et al., Symp. VLSI Tech. Dig., p. 40, 2006.
4. Yong-Sung Kim et al., IEDM Tech. Dig., p. 315, 2005.
5. Hiroshi Kujirai et al., IEDM Tech. Dig., p. 395, 2001.
6. Sun-Ghil Lee et al., Proc. of ESSDERC, p. 309, 2005.