Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 48-49

  Yasutake, N ^a   Azuma, A ^a   Ishida, T ^a   Kusunoki, N ^a   Mori, S ^a   Itokawa, H ^a   Mizushima, I ^a   Okamoto, S ^a   Morooka, T ^a   Aoki, N ^a   Kawanaka, S ^a   Inaba, S ^a   Toyoshima, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; OPTIMIZATION; SEMICONDUCTING GERMANIUM COMPOUNDS; SILICON ALLOYS; STRUCTURAL OPTIMIZATION; TECHNOLOGY;

DEFECT CONTROL; HIGH DRIVE CURRENT; PMOSFET; SOURCE AND DRAIN (S/D); VLSI TECHNOLOGIES;

MOSFET DEVICES;

EID: 47249132037     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339722     Document Type: Conference Paper

References (5)

1. N.Yasutakeetal., ESSDERC, pp. 77-80, 2006.
2. H. Ohta et al., IEDM Tech. Dig., pp. 247-250, 2005.
3. J.-P Han et al., IEDM Tech. Dig., pp. 59-62, 2006.
4. Y. Tateshita et al., IEDM Tech. Dig., pp. 63-66, 2006.
5. Howard C.-H. Wang et al., IEDM Tech. Dig., pp. 67-70, 2006.