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Volumn , Issue , 2007, Pages 1-2
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Compiling code accelerators for FPGAs
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Author keywords
FPGA code acceleration
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Indexed keywords
ACCELERATION;
CLOCKS;
CODES (SYMBOLS);
COMMERCE;
COMPUTATION THEORY;
COMPUTER CIRCUITS;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
DIGITAL STORAGE;
EFFICIENCY;
EMBEDDED SYSTEMS;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
HIGH LEVEL SYNTHESIS;
IMAGE CODING;
INTEGRATED CIRCUIT DESIGN;
LOGIC DESIGN;
PARALLEL PROCESSING SYSTEMS;
PROGRAM COMPILERS;
PROGRAM TRANSLATORS;
TRANSLATION (LANGUAGES);
ALGORITHM IMPLEMENTATION;
APPLICATION DEVELOPERS;
ARCHITECTURAL STRUCTURE;
ELECTRONIC DESIGN AUTOMATION TOOLS;
FPGA CODE ACCELERATION;
LOOP-LEVEL PARALLELISM;
MULTIDIMENSIONAL ARRAYS;
RESEARCH AND DEVELOPMENT;
C (PROGRAMMING LANGUAGE);
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EID: 47149090590
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/1289881.1289882 Document Type: Conference Paper |
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Times cited : (4)
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References (0)
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