A 53.3 Mb/s 4×4 16-QAM MIMO Decoder in 0.35-μm CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4947-4950

  Guo, Zhan ^a   Nilsson, Peter ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CMOS TECHNOLOGY; CORE AREA; LOW COMPLEXITY; LOW POWER; POWER CONSUMPTION; SCHNORR-EUCHNER DECODER; VLSI ARCHITECTURES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; MULTIPLEXING; QUADRATURE AMPLITUDE MODULATION;

DECODING;

EID: 47049120210     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465743     Document Type: Conference Paper

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