A defect-tolerant architecture for nanoelectronic resistive memories

7th Annual Non-Volatile Memory Technology Symposium, NVMTS

Volumn , Issue , 2006, Pages 58-63

  Strukov, Dmitri B ^a   Likharev, Konstantin K ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; FLASH MEMORY; NONVOLATILE STORAGE; SEMICONDUCTOR STORAGE;

ACCESS TIME; BIT DENSITY; DEFECT-TOLERANT ARCHITECTURES; ERROR CORRECTING CODE; HYBRID CIRCUIT; NANO-DEVICES; RESISTIVE MEMORY; SEMICONDUCTOR MEMORY;

MEMORY ARCHITECTURE;

EID: 46849100458     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/nvmt.2006.378878     Document Type: Conference Paper

References (19)

1. International Technology Roadmap for Semiconductors. 2005 Edition, available online at http://public.itrs.net/.
2. D. B. Strukov and K. K. Likharev, "Defect tolerant architectures for nanoelectronic crossbar memories," J. Nanosci. Nanotechnol., 2006, in press.
3. W. Wu, et al., "One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography," App. Phys. A-Mater. Sci. Process., vol. 80, no. 6, pp. 1173-1178, 2005.
4. Y. S. Lai, et al., "Bistable resistance switching of poly(n-vinylcarbazole) films for nonvolatile memory applications," Applied Physics Letters, vol. 87, no. 12, p. 122101, 2005.
5. Y.-C. Chen, et al., "An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device," IEDM Tech. Digest, p. 37.4.1, 2003.
6. A. Chen, et al., "Non-volatile resistive switching for advanced memory applications," IEDM Tech. Digest, p. 31.3, 2005.
7. K. K. Likharev and D. B. Strukov, "CMOL: Devices, circuits, and architectures," in Introducing Molecular Electronics, G. Cuniberti, et al., Eds. Berlin: Springer, 2005, pp. 447-478.
8. A. DeHon and K. Likharev, "Hybrid CMOS/nanoelectronic digital circuits: Devices, architectures, and design automation," in ICCAD-2005, 2005, pp. 375-382.
9. P. J. Kuekes, et al., "Crossbar nanocomputers," Sci., Am., vol. 293, no. 5, pp. 72-80, 2005.
10. M. Bender, et al., "Status and prospects of uv-nanoimprint technology," Microel. Eng., vol. 83, no. 4-9, pp. 827-830, 2006.
11. H. H. Solak, "Nanolithography with coherent extreme ultraviolet light," J. Phys. D, vol. 39, no. 10, pp. R171-R188, 2006.
12. K. K. Likharev, "Electronics below 10 nm," in Nano and Giga Challenges in Microelectronics. Amsterdam: Elsevier, 2003, pp. 27-68.
13. K. K. Likharev, et al., "CrossNets - High-performance neuromorphic architectures for CMOL circuits," Ann. NY Acad. Sci., vol. 1006, pp. 146-163, 2003.
14. S. Fölling, et al., "Single-electron latching switches as nanoscale synapses," in IJCNN'01. Mount Royal, NY: Int. Neural Network Soc., 2001, pp. 216-221.
15. R. E. Blahut, Algebraic Codes for Data Transmission. Cambridge: Cambridge University Press, 2003.
16. D. B. Strukov and K. K. Likharev, "Prospects for terabit-scale nanoelectronic memories," Nanotechnology, vol. 16, pp. 137-148, 2005.
17. C. H. Stapper and H. S. Lee, "Synergistic fault-tolerance for memory chips," IEEE Trans. Comput., vol. 41, no. 9, pp. 1078-1087, 1992.
18. D. B. Strukov and K. K. Likharev, "CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 6, pp. 888-900, 2005.
19. G.-L. Ingold and Y. V. Nazarov, "Charge tunneling rates in ultrasmall junctions," in Single Charge Tunneling, H. Grabert and M. H. Devoret, Eds. New York: Plenum Press, 1992, vol. 294, pp. 21-107.