Faster floating-point square root for integer processors

2007 Symposium on Industrial Embedded Systems Proceeedings, SIES'2007

Volumn , Issue , 2007, Pages 324-327

  Jeannerod, Claude Pierre ^b   Knochenl, Hervé ^c   Monat, Christophe ^a,c   Revy, Guillaume ^b  

^a IEEE

^b UNIVERSITÉ DE LYON   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; DIGITAL ARITHMETIC; INTEGRATED CIRCUITS;

ARCHITECTURAL FEATURES; CORRECT ROUNDING; DESIGN CODES; FLOATING POINT (FP); FLOATING POINT ARITHMETICS; INTEGER PROCESSORS; INTERNATIONAL SYMPOSIUM; SQUARE ROOTING; WORK-IN-PROGRESS (WIP);

EMBEDDED SYSTEMS;

EID: 46749133194     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIES.2007.4297353     Document Type: Conference Paper

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