An 11-Bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 7, 2008, Pages 1626-1637

  Ahmed, Imran ^a,b   Johns, David A ^a,b  

^a IEEE

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

ADC; Analog to digital conversion; Background; Calibration; Capacitor mismatch; CMOS; DAC; Dual ADC; Missing codes; Pipeline; Rapid; Split ADC

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ERRORS; MULTICARRIER MODULATION; OPTICAL DESIGN; PIPELINES;

CMOS PROCESSING; DIGITAL BACKGROUND; GAIN ERRORS; MULTI-BIT; PIPELINED ADC; PROOF-OF-CONCEPT (POC);

CALIBRATION;

EID: 46749116777     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.923724     Document Type: Conference Paper

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