An analog CMOS double-edge multi-phase low-latency pulse width modulator

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn , Issue , 2007, Pages 355-360

  Zhang, Jianhui ^a   Sanders, Seth R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUNTING CIRCUITS; EXHIBITIONS; MODULATION; POWER ELECTRONICS; PULSE MODULATION; REAL TIME SYSTEMS; WIRELESS SENSOR NETWORKS;

(+ MOD 2N) OPERATION; ACTIVE CHIP AREA; ANALOG CMOS; APPLIED (CO); AVERAGE FREQUENCY; CMOS PROCESSING; DUTY CYCLES; DUTY RATIO; FEEDBACK VOLTAGES; HIGH PRECISION; INPUT VOLTAGES; LOW LATENCY; MULTI-PHASE; NOISE IMMUNITY; PHASE DIFFERENCES; PULSE-WIDTH MODULATORS; RING OSCILLATORS;

PULSE WIDTH MODULATION;

EID: 46449107272     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEX.2007.357538     Document Type: Conference Paper

References (5)

1. A. V. Peterchev and S. R. Sanders, "Design of ceramic-capacitor VRM's with estimated load current feedforward," in Proc. IEEE Power Electron. Spec. Conf., 2004, pp. 4325-4332.
2. G. Hanington, P.F.Chen, P.Asbeck, and L.E.Larson, "High-efficiency power amplifier using power supply voltage for CDMA applications," IEEE Transactions on Microwave theory and Techniques, vol. 47, pp. 1471-1476, August 1999.
3. th ed. New York: Wiely, 2001.
4. H. Khorramabadi, "A CMOS line driver with 90db linearity for ISDN application," IEEE Journal of Solid-Stage Circuits, vol. 27, pp. 539-544, April 1992.
5. J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, "A 4 μA quiescent current dual-mode digitally controlled buck converter IC for cellular phone applications," IEEE Journal of Solid-Stage Circuits, vol. 39, no. 12, pp. 2342-2348, December 2004.