Test methodology for low power VLSI neural oscillator circuit

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 2, Issue , 2004, Pages 1546-1550

  Lee, Young Jun ^a   Lee, Jihyun ^a   Heo, Jaeyoung ^a   Zhang, Fengming ^a   Kim, Yong Bin ^a   Lombardi, F ^a  

^a NORTHEASTERN UNIVERSITY   (United States)

Author keywords

Chaotic; Chemical synapse; Comparator; Electronic neuron; Subthreshold; Tanh; Test methodology

Indexed keywords

CHEMICAL SYNAPSE; COMPARATORS; ELECTRONIC NEURONS; SUBTHRESHOLD; TANH; TEST METHODOLOGY;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIFFERENTIAL EQUATIONS; ELECTRIC POWER SYSTEMS; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); SILICON;

VLSI CIRCUITS;

EID: 4644309587     PISSN: 10915281     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMTC.2004.1351360     Document Type: Conference Paper

References (6)

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2. R.D. Pinto, P. Varona, et al. Synchronous behavior of two coupled electronic neurons, Physical Review E, Vol. 62, No.2, Aug. 2000, pp.2644-2656.
3. Young Jun Lee, Jihyun Lee, et al, Law Power Real Time Electronic Neuron VLSI Design Using Subthreshold Technique, Submitted to ISCAS 2004.
4. C. Mead, Anafog VLSI and Neural Systems, Addison Wesley, 1989.
5. P.E. Allen, D.R. Holberg, "CMOS Analog Integrated Circuit Design", Oxford University Press, 1987.
6. www.mathworks.com/access/helpdesk_r12pI/help/toolbox/simulink/ug/ getting3.shtml Simulink on-line Manual, Mathworks, co.