A new route for cost-effective multi-process assembly of an optical silicon bench at the sub-micron accuracy

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn 29, Issue , 2004, Pages 158-159

  Lecarpentier, Gilbert ^a   Paris, Bertrand ^b   Rabaron, Stéphane ^b  

^a SUSS MicroTec Lithography GmbH   (United States)

^b Avanex France ^*  (France)

Author keywords

[No Author keywords available]

Indexed keywords

MULTI-PROCESS ASSEMBLY; OPTICAL SILICON BENCH; PLANAR TECHNOLOGY; SUB-MICRON ACCURACY;

AUTOMATION; BONDING; COST EFFECTIVENESS; OPTIMIZATION; PROBES; SEMICONDUCTOR LASERS; SIGNAL PROCESSING; SILICON; TELECOMMUNICATION;

OPTOELECTRONIC DEVICES;

EID: 4644240664     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Reygrobellet J.N. et al. < High reliability 2.5 Gbit/s modules using silicon platform technology. ECTC 53rd, 2003, pp. 284-289.