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Volumn 51, Issue 1, 2004, Pages 191-195

A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; MOSFET DEVICES; SEQUENTIAL SWITCHING; SYSTEMATIC ERRORS;

EID: 4644231894     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.821307     Document Type: Article
Times cited : (48)

References (9)
  • 2
    • 0022891057 scopus 로고
    • Characterization and modeling of mismatch in MOS transistors for precision analog design
    • Dec
    • K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1065, Dec. 1986.
    • (1986) IEEE J. Solid-State Circuits , vol.SC-21 , pp. 1057-1065
    • Lakshmikumar, K.R.1    Hadaway, R.A.2    Copeland, M.A.3
  • 6
  • 8
    • 0034229950 scopus 로고    scopus 로고
    • Switching-sequence optimization for gradient error-compensation in thermometer-decoded DAC array
    • July
    • Y. Cong and R. L. Geiger, "Switching-Sequence optimization for gradient error-compensation in thermometer-decoded DAC array," IEEE Trans. Circuits Syst. II, vol. 47, pp. 585-595, July 2000.
    • (2000) IEEE Trans. Circuits Syst. II , vol.47 , pp. 585-595
    • Cong, Y.1    Geiger, R.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.