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Volumn , Issue , 2006, Pages 821-824
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An alternative to sequential architectures to improve the processing time of passive stereovision algorithms
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Author keywords
[No Author keywords available]
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Indexed keywords
DIGITAL SIGNAL PROCESSORS;
FUZZY LOGIC;
PARALLEL ALGORITHMS;
PIPELINES;
VISUAL COMMUNICATION;
AND PIPELINES;
FIELD PROGRAMMABLE LOGIC (FPL);
FPGA CIRCUITS;
HARVARD;
INTERNATIONAL CONFERENCES;
PARALLEL ARCHITECTURES;
PROCESSING TIME;
REAL TIME PROCESSING;
REAL TIME VISION;
STEREO VISION;
STEREO VISION SENSORS;
ULTRA-FAST;
REAL TIME SYSTEMS;
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EID: 46249122150
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/FPL.2006.311322 Document Type: Conference Paper |
Times cited : (8)
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References (6)
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