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Volumn , Issue , 2006, Pages 297-302

Thermal-induced leakage power optimization by redundant resource allocation

Author keywords

[No Author keywords available]

Indexed keywords

BEST SOLUTION; COMPUTER-AIDED DESIGN; DESIGN STAGES; GENERAL (CO); HOT-SPOTS; INTERNATIONAL CONFERENCES; LEAKAGE MODELS; LEAKAGE POWER; LEAKAGE POWER OPTIMIZATION; LOW LEAKAGE; LOW POWERS; LOW-POWER DESIGNS; ON CHIP TEMPERATURE; OPERATING CONDITIONS; OPTIMAL NUMBER; OPTIMAL RESOURCE; OPTIMAL VALUES; POWER DENSITY (PD); RESOURCE BINDING; RESOURCE USAGE; STARTING POINTS;

EID: 46149106383     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320049     Document Type: Conference Paper
Times cited : (18)

References (16)
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  • 2
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  • 6
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    • Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction
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  • 7
    • 0034452632 scopus 로고    scopus 로고
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    • Anaheim. CA, June
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  • 11
    • 1542359159 scopus 로고    scopus 로고
    • Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization
    • Seoul, Korea, August
    • D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, D. Chinnery, B. Thompson, and K. Keutzer. Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization. In ISLPED, Seoul, Korea, August 2003.
    • (2003) ISLPED
    • Nguyen, D.1    Davare, A.2    Orshansky, M.3    Chinnery, D.4    Chinnery, D.5    Thompson, B.6    Keutzer, K.7
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  • 13
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.