Hardware-based TCP processor for gigabit ethernet

IEEE Transactions on Nuclear Science

Volumn 55, Issue 3, 2008, Pages 1631-1637

  Uchida, Tomohisa ^a,b  

^a IEEE

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Ethernet; FPGA; TCP IP

Indexed keywords

COMPUTER SOFTWARE; CONTROL EQUIPMENT; CONTROL SYSTEMS; ETHERNET; INTERNET PROTOCOLS; STANDARDS; TELECOMMUNICATION NETWORKS; THROUGHPUT; TRANSMISSION CONTROL PROTOCOL;

CIRCUIT SIZE; DE FACTO STANDARDS; FIELD PROGRAMMABLE GATE ARRAY (FPGA); FRONT END DEVICES; GIGA BIT ETHERNET (GBE); OPERATING SYSTEMS (OS); PERIPHERAL (SPI); PHYSICAL LAYER DEVICE (PHY); SLOW CONTROL; SMALL DEVICES; TCP THROUGHPUT; TRANSMISSION CONTROL PROTOCOL (TCP); UPPER LIMITS; USER DATAGRAM PROTOCOL (UDP);

LOCAL AREA NETWORKS;

EID: 45849118748     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2008.920264     Document Type: Conference Paper

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