Low-power current mode logic for improved DPA-resistance in embedded systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1059-1062

  Toprak, Zeynep ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS GATE; CMOS TECHNOLOGY; DATA SECURITY; HIGH NOISE; INPUT PATTERNS; LOW NOISE; LOW POWER; LOW-SPEED APPLICATIONS; MIXED SIGNAL APPLICATIONS; MOS CURRENT-MODE LOGIC; ORDERS OF MAGNITUDE; POWER SUPPLY;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; SMART CARDS;

SECURITY OF DATA;

EID: 45749134245     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464774     Document Type: Conference Paper

References (9)

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8. K. Tiri et al. Securing encryption algorithms against DPA at the logic level: Next generation smart card technology. In CHES 2003, pages 125- 136. Sept. 2003.
9. M. Yamashina et al. An MOS current mode logic (MCML) circuit for low-power sub-GHz processors. IEICE Transactions on Electronics, E75- C(10):1181-87, Oct. 1992.