Designing packet buffers for router linecards

IEEE/ACM Transactions on Networking

Volumn 16, Issue 3, 2008, Pages 705-717

  Iyer, Sundar ^a   Kompella, Ramana Rao ^b   McKeown, Nick ^a  

^a Stanford University   (United States)

^b Purdue University   (United States)

Author keywords

Cache; Hit rate; Line card; Memory hierarchy; Packet buffer; Router; Switches

Indexed keywords

ARCHITECTURAL DESIGN; COMPUTERS; DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; INFORMATION TECHNOLOGY; MECHANICS; NUMERICAL METHODS; PIPELINES; ROUTERS; SILICON; STATIC RANDOM ACCESS STORAGE; SWITCHES;

(100) SILICON; (I ,J) CONDITIONS; 10 GB/ S; ACCESS TIME; COMPUTER INDUSTRIES; DYNAMIC ALLOCATIONS; EQUIPMENT VENDORS; ETHERNET SWITCHING; EXTERNAL MEMORIES; FIRST INPUT FIRST OUTPUT (FIFO) QUEUES; INTERNET ROUTERS; LINE CARDS; LOW POWERS; LOWER BOUNDS; MISS RATES; PACKET BUFFERING; PACKET SWITCHES;

COMPUTER NETWORKS;

EID: 45749128633     PISSN: 10636692     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNET.2008.923720     Document Type: Article

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