Common-mode backchannel signaling system for differential high-speed links

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 352-355

  Ho, Andrew ^a   Stojanović, Vladimir ^a,b   Chen, Fred ^a   Werner, Carl ^a   Tsang, Grace ^a   Alon, Elad ^a,b   Kollipara, Ravi ^a   Zerbe, Jared ^a   Horowitz, Mark A ^b  

^a RAMBUS INC   (United States)

^b Stanford University   (United States)

Author keywords

Backchannel; Common mode; High speed links

Indexed keywords

BANDWIDTH; CROSSTALK; EQUALIZERS; RELIABILITY; SPURIOUS SIGNAL NOISE; TRANSCEIVERS; TRANSFER FUNCTIONS;

BACKCHANNEL; CENTRALIZED CONTROL; COMMON-MODE; HIGH-SPEED LINKS;

SIGNAL PROCESSING;

EID: 4544382853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. V. Stojanovic et. al, "Adaptive Equalization and Data Recovery in a Dual-Mode (PAM2/4) Serial Link Transceiver," to be published.
2. J.T. Stonick et. al, "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS," IEEE Journal of Solid-State Circuits, Mar. 2003
3. T Gabara, "Phantom Mode Signaling in VLSI Systems," Conference on Advanced Research in VLSI, Mar. 2001
4. J. Zerbe et al, "Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell," IEEE International Solid-State Circuits Conference, Feb. 2003, San Francisco.