Evidence for source side injection hot carrier effects on lateral DMOS transistors

Microelectronics Reliability

Volumn 44, Issue 9-11 SPEC. ISS., 2004, Pages 1621-1624

  Aresu, S ^b   De Ceuninck, W ^a,b   Van Den Bosch, G ^b   Groeseneken, G ^b,c   Moens, P ^d   Manca, J ^a,b   Wojciechowski, D ^d   Gassot, P ^d  

^a HASSELT UNIVERSITY   (Belgium)

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d ON SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEGRADATION; ELECTRIC FIELDS; ELECTRIC POTENTIAL; ELECTRON MOBILITY; ELECTRON TRAPS; GATES (TRANSISTOR); STRESS ANALYSIS; TEMPERATURE DISTRIBUTION; TRANSISTORS;

CARRIER DEGRADATION; CHARGE PUMPING (CP); DMOS TRANSISTORS; SOURCE SIDE INJECTION (SSI);

MOS DEVICES;

EID: 4544378764     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.07.080     Document Type: Conference Paper

References (4)

1. H. Ballan, M. Declercq, "High Voltage Devices and Circuits in Standard CMOS Technologies", Kluwer Academic Publishers.
2. In-situ method patented by the LUC and IMEC, No. PCT/EP90/00291, April 19, 1990.
3. P. Moens et al., "A Novel Hot-Hole Injection Degradation Model for Lateral nDMOS Transistors", IEDM Techn. Dig., 2001, pp877-880.
4. C.T. Wang "Hot carrier design considerations for MOS Devices and circuits" PhD edit by Van Nostrand Reinhold, New York, 1992.