System-level design techniques for throughput and power optimization of multiprocessor SoC architectures

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 39-45

  Srinivasan, Krishnan ^a   Telkar, Nagender ^a   Ramamurthi, Vijay ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOOP TRANSFORMATION; POWER CONSUMPTION; SYSTEM-LEVEL DESIGN TECHNIQUES; SYSTEM-ON-CHIP (SOC) ARCHITECTURE;

APPROXIMATION THEORY; COMPUTER AIDED DESIGN; ELECTRIC POTENTIAL; FREQUENCIES; HEURISTIC METHODS; MAPPING; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; OPTIMIZATION; THROUGHPUT;

MULTIPROCESSING SYSTEMS;

EID: 4544375965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2004.1339506     Document Type: Conference Paper

References (20)

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