Characterization and debug of reverse-body bias low-power modes

Electronic Device Failure Analysis

Volumn 6, Issue 1, 2004, Pages 13-21

  Clark, Lawrence T ^a,c,d   McCarroll, David W ^b,e   Bawolek, Edward J ^b,f  

^a UNIVERSITY OF NEW MEXICO   (United States)

^b INTEL CORPORATION   (United States)

^c NORTHERN ARIZONA UNIVERSITY   (United States)

^d ARIZONA STATE UNIVERSITY   (United States)

^e TEXAS A AND M UNIVERSITY   (United States)

^f UNIVERSITY OF ARIZONA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED VOLTAGES; BODY BIAS; CHANNEL EDGES; DESIGN ERRORS; DESIGN PROJECTS; DIFFERENT PROCESS; GATE DRAIN; GATE-INDUCED DRAIN LEAKAGE; HALO DOPING; LARGE ARRAYS; LOW CURRENTS; LOW-POWER MODE; PROCESS TECHNOLOGIES; TECHNOLOGY NODES; TRANSISTOR SCALING; TUNNELING CURRENT;

DESIGN;

DRAIN CURRENT;

EID: 4544356232     PISSN: 15370755     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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