Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 178-179

  Lallement, F ^a   Duriez, B ^b   Grouillet, A ^a   Arnaud, F ^a   Tavel, B ^b   Wacquant, F ^a   Stolk, P ^b   Woo, M ^c   Erokhin, Y ^d   Scheuer, J ^d   Godet, L ^d   Weeman, J ^d   Distaso, D ^d   Lenoble, D ^a  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

^c MOTOROLA INC   (United States)

^d Varian SEA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ANALYSIS; ANNEALING; BORON; CAPACITANCE; DATA REDUCTION; DIELECTRIC MATERIALS; DIFFUSION; ELECTRIC POTENTIAL; FABRICATION; LEAKAGE CURRENTS; OPTIMIZATION; PERFORMANCE; TEMPERATURE;

ACTIVATION TEMPERATURES; DESIGNS OF EXPERIMENTS (DOE); PLASMA DOPING; SOURCE-DRAIN EXTENSIONS (SDE);

CMOS INTEGRATED CIRCUITS;

EID: 4544336610     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345465     Document Type: Conference Paper

References (2)

1. J.O. Borland, MRS Symp. Proc., 202
2. T. Ito, et al., VLSI Symp. Tech. Dig., 2003