A 2.4GHz low-power low-phase-noise CMOS LC VCO

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 213-214

  Long, Jie ^a   Foo, Jo Yi ^a   Weber, Robert J ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC INDUCTORS; ELECTRIC RESISTANCE; MAGNETIC COUPLINGS; MATHEMATICAL MODELS; OPTIMIZATION; OSCILLATORS (ELECTRONIC); PRODUCT DESIGN; Q FACTOR MEASUREMENT; RESONANCE; TOPOLOGY;

MIXED-SIGNAL CMOS; PHASE NOISE; SPIRAL INDUCTORS;

CMOS INTEGRATED CIRCUITS;

EID: 4544334654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M.Tiebout, "Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS," IEEE J.Solid-State Circuits,vol.36, No.7, pp.1018-1024, July 2001.
2. T.I.Ahrens, A.Hajimiri and T.H.Lee, "A 1.6GHz 0.5mW CMOS LC low phase noise VCO using bond wire inductance", in Proc. 1997 Intl. Workshop on De-sign of Mixed-Mode Integrated Circuits and Applications, pp.69-71, Jul.l997.
3. T.I.Ahrens and T.H.Lee, "A 1.4GHz 3mW CMOS LC low phase noise VCO using tapped bond wire induc-tances", in Proc. 1998 Law Power Electronics and Design, pp. 16-19, Aug.1998.
4. R.Dehghani and S.M. Atarodi, "Optimised analytic de-signed 2.5GHz CMOS VCO", Elec. Letters, vol.39, No.16, pp.1160-1162, Aug.2003.