Multi-clock timed networks

Proceedings - Symposium on Logic in Computer Science

Volumn 19, Issue , 2004, Pages 345-354

  Abdulla, Parosh Aziz ^a   Deneux, Johann ^a   Mahata, Pritha ^a  

^a UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

FINITE STATE PROCESSES (FSP); PARAMETRIC REASONING; TIMED NETWORKS;

AUTOMATA THEORY; AUTOMATION; CLOCKS; COMPUTER SCIENCE; COMPUTER SIMULATION; ENCODING (SYMBOLS); MATHEMATICAL MODELS; MATHEMATICAL OPERATORS; PROBLEM SOLVING; REAL TIME SYSTEMS;

COMPUTER NETWORKS;

EID: 4544311549     PISSN: 10436871     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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