A novel MNOS technology using gate hole injection in erase operation for embedded nonvolatile memory applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 80-81

  Ito, F ^a   Kawashima, Y ^a   Sakai, T ^a   Kanamaru, Y ^a   Ishii, Y ^a   Mizuno, M ^a   Hashimoto, T ^a   Ishimaru, T ^b   Mine, T ^b   Matsuzaki, N ^b   Kume, H ^b   Tanaka, T ^a   Shinagawa, Y ^a   Toya, T ^a   Okuyama, K ^a   Kuroda, K ^a   Kubota, K ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Interface trap; Memory; MNOS; MONOS; Nonvolatile

Indexed keywords

ELECTRIC FIELD EFFECTS; ELECTRON TRAPS; ELECTRON TUNNELING; FABRICATION; FLASH MEMORY; GATES (TRANSISTOR); MOS DEVICES; SILICON NITRIDE;

CHARGE TRAPPING; MNOS TECHNOLOGY; NONVOLATILE MEMORY; OXIDE FILMS;

DATA STORAGE EQUIPMENT;

EID: 4544291580     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345404     Document Type: Conference Paper

References (4)

1. S. Minami and Y. Kamigaki, IEEE Trans. on Elec. Dev., vol. 40, p.2011-2017, 1993.
2. B. Eitan, et al., IEEE Elec. Dev. Lett., vol. 21 No. 11, p.543-545, 2000.
3. T. Tanaka, et al., VLSI Circuits Dig. p.221-222, 2003.
4. N. Matsuzaki, et al., Ext. Abst. SSDM p.204-205, 2003.