Overlay metrology sampling capability analysis and implementation in manufacturing

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2004, Pages 208-212

  Sullivan, Daniel B ^a   Conrad, Edward W ^a   Smyth, John S ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

APC; Lithography; Metrology; Overlay; Skip lot sample plans

Indexed keywords

MEASUREMENT THEORY; PHOTOLITHOGRAPHY; PROCESS ENGINEERING; RISK ASSESSMENT; SAMPLING; STATISTICAL METHODS; STATISTICAL PROCESS CONTROL;

APC FILTERING; OVERLAYS; SKIP LOT SAMPLE PLANS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 4544290552     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Fink, I.D., Sullivan, N.T., Lekas, J.S., Overlay sample plan optimization for the detection of higher order contributions to misalignment, SPIE Proceedings, Volume 2196, pp.389-399, 1994
2. rd Edition, John Wiley & Sons, Inc., New York, pp. 440-448, 1997
3. Royston, P., Algorithm ASR94 (SWILK sub routine) Applied Statistics Journal, Volume 44, No. 4, 1995
4. Shapiro, S. S., How to Test Normality and Other Distributional Assumptions, Vol. 3, The ASQC Basic References in Quality Control: Statistical Techniques, ASQC, Milwaukee, Wis., pp. 21-24, 199.