FPGA placement and routing using particle swarm optimization

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 307-308

  Gudise, Venu G ^a   Venayagamoorthy, Ganesh K ^a  

^a Architectural and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC LOGIC UNITS; LOGIC ELEMENTS; OPTIMAL POSITION VECTORS; PARTICLE SWARM OPTIMIZATION (PSO);

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DIGITAL CIRCUITS; FORMAL LOGIC; HEATING; OPTIMIZATION; PARTICLE ACCELERATORS; PROBLEM SOLVING; ROUTERS; SIMULATED ANNEALING; VECTORS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 4544282705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2004.1339567     Document Type: Conference Paper

References (4)

1. S. K. Nag, R. A. Rutenbar, "Performance-Driven Simultaneous Placement and Routing for FPGA's," IEEE Transactions on Computer-Aided design of integrated circuits and systems, Vol. 17:6, June 1998, pp. 499-518.
2. J. Kennedy, Russell C. Eberhart, Yuhui Shi, Swarm Intelligence, Morgan Kaufmann Publishers, 2001.
3. V. G. Gudise, G. K. Venayagamoorthy, "Evolving Digital Circuits Using Particle Swarm," International Joint Conference on Neural Networks, July 2003, pp. 468-472.
4. K. Hwang, Computer Arithmetic: Principles, Architecture and Design, John Wiley & Sons, 1979, ISBN 0-471-03496-7.