Fully Pipelined TSPC Barrel Shifter for High-Speed Applications

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 6, 1995, Pages 686-690

  Pereira, R ^a   Michell, J A ^a   Solana, J M ^a  

^a UNIVERSITY OF CANTABRIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 4544281290     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.387073     Document Type: Article

References (8)

1. J. A. Michell, A. M. Burón, J. M. Solana, and G. Ruiz, “VLSI data-path structure for a pipeline 2D-FHT implementation,” in Signal Processing V: Theories and Applications. Elsevier Science Publishers B.V., 1990, pp. 1575–1578.
2. G. A. Asato, C. Ditzen, and S. Dholakia, “A data-path multiplier with automatic insertion of pipeline stages,” IEEE J. Solid-State Circuits, vol. 25, pp. 383–387, Apr. 1990.
3. Y. Ji-Ren, I. Karlsson, and C. Svensson, “A true single-phase-clock dynamic CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 899–901, Oct. 1987.
4. J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62–70, Feb. 1989.
5. S. M. Kang, “Domino–CMOS barrel switch for 32-bit VLSI processors,” IEEE Circuits and Devices Mag., pp. 3–8, May 1987.
6. G. M. Tharakan and S. M. Kang, “A new design of a fast barrel switch network,” IEEE J. Solid-State Circuits, vol. 27, pp. 217–221, Feb. 1992.
7. R. Pereira, J. A. Michell, and J. M. Solana, “Pipelined TSPC barrel shifter with scan test facilities for VLSI implementation of high speed DSP applications,” in Proc. EURO ASIC-92 Conf., IEEE Computer Society Press, June 1992, pp. 405–406.
8. G. Ruiz, D. Herrero, J. A. Michell, and A. M. Burón, “Electrical simulator for gate oxide shorts and resistive shorts in MOS digital circuits,” in Proc. IXIASTED Int. Conf. Applied Informatics, Acta Press, May 1993, pp. 91–94.