Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO 2) gate dielectric

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 106-107

  Thean, A V Y ^a   Vandooren, A ^a   Kalpat, S ^a   Du, Y ^a   To, I ^a   Hughes, J ^a   Stephens, T ^a   Goolsby, B ^a   White, T ^a   Barr, A ^a   Mathew, L ^a   Huang, M ^a   Egley, S ^a   Zavala, M ^a   Eades, D ^a   Sphabmixay, K ^b   Schaeffer, J ^a   Triyoso, D ^a   Rossow, M ^a   Roan, D ^a   Pham, D ^a   Rai, R ^a   Murphy, S ^a   Nguyen, B Y ^a   White, B E ^a   Duvallet, A ^a   Dao, T ^a   Mogab, J ^a   more..

^a MOTOROLA INC   (United States)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAUER DEPOSITION; GATE DIELECTRIC; PARTIALLY-DEPLETED DEVICES; SILICON-ON-INSULATOR (SOI);

ACOUSTIC NOISE; DEGRADATION; DIELECTRIC AMPLIFIERS; ELECTRIC INSULATORS; HOLE MOBILITY; NITROGEN COMPOUNDS; OPTIMIZATION; RELIABILITY; SILICON COMPOUNDS; TANTALUM COMPOUNDS; TRANSITION METALS;

GATES (TRANSISTOR);

EID: 4544229587     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Yoshimi et al., IEEE Trans. Electron Devices, vol. 36, pp. 493-503, 1989.
2. S. Samavedam et al., Proc. 2002 Symposium on VLSI Technology, p.24-25.
3. A. Blaum et. al, Proc. IEEE 2001 ICMTS, pp. 125-130, March 2001