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Volumn 12, Issue 3, 2004, Pages 327-353

Effective memetic algorithms for VLSI design = genetic algorithms + local search + multi-level clustering

Author keywords

Circuit Placement; Genetic Algorithms; Local Search; Memetic Algorithms; Multi Level Clustering; Netlist Partitioning

Indexed keywords

CIRCUIT PLACEMENT; LOCAL SEARCH; MEMETIC ALGORITHMS (MA); MULTI-LEVEL CLUSTERING; NETLIST PARTITIONING;

EID: 4544226146     PISSN: 10636560     EISSN: None     Source Type: Journal    
DOI: 10.1162/1063656041774947     Document Type: Article
Times cited : (42)

References (24)
  • 1
    • 35048814272 scopus 로고    scopus 로고
    • An integrated genetic algorithm with dynamic hill climbing for VLSI circuit partitioning
    • Las Vegas, Nevada. IEEE
    • Areibi, S. (2000). An Integrated Genetic Algorithm With Dynamic Hill Climbing for VLSI Circuit Partitioning. In GECCO 2000, pages 97-102, Las Vegas, Nevada. IEEE.
    • (2000) GECCO 2000 , pp. 97-102
    • Areibi, S.1
  • 2
    • 4544226607 scopus 로고    scopus 로고
    • A comparison of genetic/memetic algorithms and other heuristic search techniques
    • (June), Las Vegas, Nevada
    • Areibi, S., Moussa, M., and Abdullah, H. (June 2001a). A Comparison of Genetic/Memetic Algorithms and Other Heuristic Search Techniques. In International Conference on Artificial Intelligence, pages 660-666, Las Vegas, Nevada.
    • (2001) International Conference on Artificial Intelligence , pp. 660-666
    • Areibi, S.1    Moussa, M.2    Abdullah, H.3
  • 3
  • 4
    • 0029716142 scopus 로고    scopus 로고
    • An efficient clustering technique for circuit partitioning
    • San Diego, California
    • Areibi, S. and Vannelli, A. (1996). An Efficient Clustering Technique for Circuit Partitioning. In IEEE ISCAS, pages 671-674, San Diego, California.
    • (1996) IEEE ISCAS , pp. 671-674
    • Areibi, S.1    Vannelli, A.2
  • 5
    • 0030421294 scopus 로고    scopus 로고
    • VLSI circuit partitioning by cluster-removal using iterative improvement techniques
    • ACM/IEEE
    • Dutt, S. and Deng, W. (1996). VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques. In IEEE International Conference on CAD, pages 194-200. ACM/IEEE.
    • (1996) IEEE International Conference on CAD , pp. 194-200
    • Dutt, S.1    Deng, W.2
  • 6
    • 0031358445 scopus 로고    scopus 로고
    • Partitioning around roadblocks: Tackling constraints with intermediate relaxations
    • November
    • Dutt, S. and Theny, H. (November 1997). Partitioning Around Roadblocks: Tackling Constraints with Intermediate Relaxations. In IEEE International Conference on CAD, pages 350-355.
    • (1997) IEEE International Conference on CAD , pp. 350-355
    • Dutt, S.1    Theny, H.2
  • 7
    • 0028510982 scopus 로고
    • A greedy randomized adaptive search procedure for the maximum independent set
    • Feo, T., Resende, M., and Smith, S. (1994). A Greedy Randomized Adaptive Search Procedure for The Maximum Ind ependent Set. Operations Research,42:860:878.
    • (1994) Operations Research , vol.42
    • Feo, T.1    Resende, M.2    Smith, S.3
  • 8
    • 85046457769 scopus 로고
    • A linear-time heuristic for improving network partitions
    • (June), Las Vegas, Nevada. ACM/IEEE
    • Fiduccia, C. and Mattheyses, R. (June 1982). A Linear-Time Heuristic for Improving Network Partitions. In Proceedings of 19th DAC, pages 175-181, Las Vegas, Nevada. ACM/IEEE.
    • (1982) Proceedings of 19th DAC , pp. 175-181
    • Fiduccia, C.1    Mattheyses, R.2
  • 13
    • 84989448763 scopus 로고
    • Automatic placement: A review of current techniques
    • Las Vegas, Nevada. IEEE/ACM
    • Karger, P. and Preas, B. (1986). Automatic Placement: A Review of Current Techniques. In Proceedings of the 23rd DAC, pages 622-629, Las Vegas, Nevada. IEEE/ACM.
    • (1986) Proceedings of the 23rd DAC , pp. 622-629
    • Karger, P.1    Preas, B.2
  • 14
    • 0030686036 scopus 로고    scopus 로고
    • Multilevel hypergraph partioning: Application in VLSI design
    • (June), Las Vegas, Nevada. ACM/IEEE
    • Karypis, G., Aggarwal, R., Kumar, V., and Shekhar, S. (June 1997). Multilevel Hypergraph Partioning: Application in VLSI Design. In Proceedings of the 35th DAC, pages 526-529, Las Vegas, Nevada. ACM/IEEE.
    • (1997) Proceedings of the 35th DAC , pp. 526-529
    • Karypis, G.1    Aggarwal, R.2    Kumar, V.3    Shekhar, S.4
  • 15
    • 84990479742 scopus 로고
    • An efficient heuristic procedure for partitioning graphs
    • February
    • Kernighan, B. and Lin, S. (February 1970). An Efficient Heuristic Procedure for Partitioning Graphs. The Bell System Technical Journal, 49(2):291-307.
    • (1970) The Bell System Technical Journal , vol.49 , Issue.2 , pp. 291-307
    • Kernighan, B.1    Lin, S.2
  • 16
    • 0024126084 scopus 로고
    • Clustering based simulated annealing for standard cell placement
    • Las Vegas, Nevada. IEEE/ACM
    • Mallela, S. and Grover, L. (1989). Clustering Based Simulated Annealing for Standard Cell Placement. In Proceedings of The 26th DAC, pages 312-317, Las Vegas, Nevada. IEEE/ACM.
    • (1989) Proceedings of the 26th DAC , pp. 312-317
    • Mallela, S.1    Grover, L.2
  • 19
    • 0028554371 scopus 로고
    • Partitioning very large circuits using analytical placement techniques
    • Las Vegas, Nevada. ACM/IEEE
    • Riess, B., Doll, K., and Johannes, F. (1994). Partitioning very large circuits using analytical placement techniques. In Proceedings of 31st DAC, pages 646-651, Las Vegas, Nevada. ACM/IEEE.
    • (1994) Proceedings of 31st DAC , pp. 646-651
    • Riess, B.1    Doll, K.2    Johannes, F.3
  • 20
    • 4544279274 scopus 로고
    • Physical design workshop 1987
    • MCNC, Marriott's Hilton Head Resort,South Carolina
    • Roberts, K. and Preas, B. (1987). Physical Design Workshop 1987. Technical report, MCNC, Marriott's Hilton Head Resort,South Carolina.
    • (1987) Technical Report
    • Roberts, K.1    Preas, B.2
  • 21
    • 0024481167 scopus 로고
    • Multiple-way network partitioning
    • January
    • Sanchis, L. (January 1989). Multiple-Way Network Partitioning. IEEE Transactions on Computers, 38(1):62-81.
    • (1989) IEEE Transactions on Computers , vol.38 , Issue.1 , pp. 62-81
    • Sanchis, L.1
  • 22
    • 0024178684 scopus 로고
    • An improved objective function for min-cut circuit partitioning
    • San Jose, California
    • Sechen, C. and Chen, D. (1988). An improved Objective Function for Min-Cut Circuit Partitioning. In Proceedings of ICCAD, pages 502-505, San Jose, California.
    • (1988) Proceedings of ICCAD , pp. 502-505
    • Sechen, C.1    Chen, D.2
  • 23
    • 84976733539 scopus 로고
    • VLSI cell placement techniques
    • Shahookar, K. and Mazumder, P. (1991). VLSI Cell Placement Techniques. ACM Computing Surveys, 23(2):143-220.
    • (1991) ACM Computing Surveys , vol.23 , Issue.2 , pp. 143-220
    • Shahookar, K.1    Mazumder, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.