Challenges with respect to high-k/metal gate stack etching and cleaning

ECS Transactions

Volumn 11, Issue 4, 2007, Pages 275-283

  Vos, R ^a   Arnauts, S ^a   Bovie, I ^a   Onsia, B ^a   Garaud, S ^a   Xu, K ^b   HongYu, Y ^a   Kubicek, S ^a   Rohr, E ^a   Schram, T ^a   Veloso, A ^a   Conard, T ^a   Leunissen, L H A ^a   Mertens, P W ^a  

^a IMEC   (Belgium)

^b SEZ AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; GATE DIELECTRICS; HIGH-K DIELECTRIC; LOGIC GATES; METAL CLEANING;

CLEANING PROPERTIES; FUTURE TECHNOLOGIES; HIGH-K/METAL GATES; INTEGRATION SCHEME; METAL GATE MATERIALS; NEW HIGH; WET-PROCESSING;

DIELECTRIC MATERIALS;

EID: 45249090596     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2779567     Document Type: Conference Paper

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