Optimized area and optimized speed hardware implementations of AES on FPGA

Proceedings - IDT'07 The 2nd International Design and Test Workshop

Volumn , Issue , 2007, Pages 207-217

  Rizk, M R M ^a   Morsy, M ^b  

^a IEEE

^b NONE

Author keywords

Architecture; Encryption; FPGA; Security processor

Indexed keywords

CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTERFACES (COMPUTER); MULTITASKING; NEODYMIUM; OPTIMIZATION; STANDARDS; TESTING; ULTRASONIC TRANSDUCERS;

ADVANCED ENCRYPTION STANDARD (AES); CRYPTO PROCESSORS; DECRYPTOR; DIGITAL DATA; HARDWARE IMPLEMENTATIONS; INTERNATIONAL DESIGNS; PIPELINED ARCHITECTURES; SECURITY PROCESSORS; SERIAL INTERFACES; XILINX VIRTEX;

ARCHITECTURAL DESIGN;

EID: 44949124495     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDT.2007.4437462     Document Type: Conference Paper

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