A low-power 4GHz comparator in 120nm CMOS technology with a technique to tune resolution

ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Volumn , Issue , 2006, Pages 320-323

  Goll, Bernhard ^a   Zimmermann, Horst ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; OPTICAL RESOLVING POWER; SWITCHING;

HIGH SWITCHING SPEED; LOGIC VOLTAGE LEVEL; STATIC POWER CONSUMPTION;

COMPARATOR CIRCUITS;

EID: 44849135567     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2006.307595     Document Type: Conference Paper

References (11)

1. H. J. M. Veendrick, "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate", IEEE J. Solid-State Circuits, vol. 15, no. 2, pp. 169-176, 1980.
2. L. Sumanen, M. Waltari, V. Hakkarainen, K. Halonen, "CMOS Dynamic Comparators for Pipeline A/D Converters", ISCAS 2002, vol. 5, pp. 157-160.
3. B. Goll, H. Zimmermann, "A Low-Power 2-GSample/s Comparator in 120 nm CMOS Technology", ESSCIRC 2005, pp. 507-510.
4. K. Uyttenhove, M. S. J. Steyaert, "A 1.8-V 6-Bit 1.3-GHz Flash ADC in 025hbox−murmm CMOS", IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1115-1122, July 2003.
5. K.-L. J. Wong, C.-K. K. Yang, "Offset Compensation in Comparators With Minimum Input-Reffered Supply Noise", IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 837-840, 2004.
6. Y.-C. Hung, B.-D. Liu, "1-V CMOS Comparator for Programmable Analog Rank-Order Extractor", IEEE Trans. Circuits and Systems, vol. 50, no. 5, pp. 673-677, 2000.
7. B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier", IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, 2004.
8. P. Amaral, J. Goes, N. Paulino, A. Steiger Garção, "An Improved Low-Voltage Low-Power CMOS Comparator to be used in High-Speed Pipeline ADCs", ISCAS 2002, vol. 5, pp. 141-144.
9. Ch. Paulus, H.-M. Blüthgen, M. Löw, E. Sicheneder, N. Brüls, A. Courtois, M. Tiebout, R. Thewes, "A 4GS/s Flash ADC in 0.13murmm CMOS", IEEE Symp. on VLSI Circuits, pp. 420-423, June 2004.
10. S. Park, Y. Palaskas, M. P. Flynn, "A 4GS/s 4b Flash ADC in 0.18murmm CMOS", ISSCC 2006, pp. 570-571.
11. A. Boni, G. Chiorboli, C. Morandi, "Dynamic characterisation of high-speed latching comparators", IEEE Electronic Letters, vol. 36, no. 5, pp. 402-404, 2000.