An 11-bit 45MS/S pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 147-150

  Ahmed, Imran ^a   Johns, David A ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ERRORS; PIPELINES;

DIGITAL BACKGROUND; EUROPEAN; MULTI-BIT; PIPELINED ADC; PROOF-OF-CONCEPT (POC); SOLID-STATE CIRCUITS CONFERENCE;

MULTICARRIER MODULATION;

EID: 44849106455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430267     Document Type: Conference Paper

References (5)

1. I. Galton, "Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters," IEEE TCAS-II. vol. 47, pp. 185-196, March 2000.
2. S. Ray, B.-S Song, "A 13-b Linear, 40-MS/s Pipelined ADC with Self-Configured Capacitor Matching", IEEE JSSC, vol 42, pp.463-474, March 2007
3. Y. Chiu, C.W.Tsang, B. Nikolic, P.R.Gray, "Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters", IEEE TCAS-I, vol 51, pp.38-46, Jan. 2004
4. J. McNeill, J. Coin, B. Larivee, "A split-ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC," ISSCC 2005, vol. I, Feb. 2005 pp. 276-598
5. J. Li, UK Moon, "Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy," IEEE TCAS-II, vol. 50, pp. 531-538, Sept. 2003