45nm/32nm CMOS - Challenge and perspective

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 32-35

  Ishimaru, Kazunari ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45 NM NODE TECHNOLOGY; 45NM NODE; 65-NM NODES; BARRIER LAYER (BL); EUROPEAN; HIGH K GATE INSULATOR; IMMERSION LITHOGRAPHY (IML); METAL GATES; NEW TECHNOLOGY DEVELOPMENT; NODE TECHNOLOGY; PERFORMANCE IMPROVEMENTS; SOLID-STATE CIRCUITS CONFERENCE;

COMPUTER NETWORKS; ELECTRON BEAM LITHOGRAPHY; MULTITASKING; NANOTECHNOLOGY; NETWORKS (CIRCUITS); TECHNOLOGICAL FORECASTING;

TECHNOLOGY;

EID: 44849105849     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430244     Document Type: Conference Paper

References (8)

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6. T. Usui, et al, Proc. of IITC, p216, 2006
7. N. Yasutake, et al, VLSI Tech. Dig., p84, 2004
8. Y. Takeyama, et al, VLSI Cir. Dig., p166, 2005