A 550mV 8dBm IIP3 4th order analog base band filter for WLAN receivers

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 504-507

  De Matteis, Marcello ^a   D'Amico, Stefano ^a   Giannini, Vito ^a,b   Baschirotto, Andrea ^a  

^a UNIVERSITY OF SALENTO   (Italy)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

EUROPEAN; SOLID-STATE CIRCUITS CONFERENCE;

EID: 44849093357     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430352     Document Type: Conference Paper

References (5)

1. A. Baschirotto and R. Castello, "A switched-op-amp SC filter with rail-rail output swing," IEEE JSSC - Dec. 1997.
2. S. Chatterjee, Y. Tsividis, P. Kinget, "A 0.5V Filter with PLL-Based Tuning in 0.18μm CMOS", Proceedings of ISSCC 2005.
3. S. Karthikeyan, S.Mortezapour, A. Tammineedi, and E. K. F. Lee "Low-Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration", IEEE Trans. on Circuits and Systems II - March 2000
4. th-order active Gm-RC reconfigurable (UMTS/WLAN) filter",IEEE JSSC,July 2006
5. J. Mahattanakul, J. Chutichatuporn, "Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme", IEEE Trans. on Circuits and Systems I, Aug. 2005.