An energy-efficient processor architecture for embedded systems

IEEE Computer Architecture Letters

Volumn 7, Issue 1, 2008, Pages 29-32

  Balfour, James ^a   Dally, William J ^a   Black Schaffer, David ^a   Parikh, Vishal ^a   Park, JongSoo ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Energy efficient embedded processor architecture; Hierarchical and distributed register organization; Instruction registers

Indexed keywords

ARCHITECTURE; CONSERVATION; DIGITAL SIGNAL PROCESSING; EFFICIENCY; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; INTEGRATED CIRCUITS; MULTITASKING; PIPELINES; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING;

COMMUNICATION RESOURCES; CONTROL LOGICS; DATA BANDWIDTHS; DATA MOVEMENTS; DISTRIBUTED DATA; EMBEDDED APPLICATIONS; ENERGY EFFICIENT; FUNCTIONAL UNITS (FU); PIPELINE REGISTERS; PROCESSOR ARCHITECTURES; PROGRAMMABLE ARCHITECTURES; REGISTER ORGANIZATION; RISC PROCESSOR (RAWE); STORAGE STRUCTURES;

DATA REDUCTION;

EID: 44849085127     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2008.1     Document Type: Article

References (16)

1. A. Gordon-Ross, S. Cotterell, and F. Vahid, "Tiny instruction caches for low power embedded systems," Transactions on Embedded Computer Systems, vol. 2, no. 4, pp. 449-481, 2003.
2. E. Grochowski and M. Annavaram, "Energy per instruction trends in Intel microprocessors," Technology@Intel Magazine, pp. 1-8, Mar. 2006.
3. S. Habnic and J. Gasisler, "Status of the LEON2/3 processor developments," in DASIA '07: DAta Systems In Aerospace 2007. The Association of European Space Industry, 2007.
4. T. R. Halfhill, "MIPS threads the needle," Microprocessor Report, February 2006.
5. S. Hines, G. Tyson, and D. Whalley, "Reducing instruction fetch cost by packing instructions into register windows," in Proc. of ACM/IEEE International Symposium on Microarchitecture, 2005.
6. S. Hsu, V. Venkatraman, S. Mathew, H. Kaul, H. Anders, S. Digne, W. Burleson, and R. Krishnamurthy, "A 2GHz 13.6.mW 12×9b multiplier for energy efficient FFT accelerators," in Proc. of the 31st European Solid-State Circuits Conference, 2005, pp. 199-202.
7. J. Kin, M. Gupta, and W. H. Mangione-Smith, "The filter cache: an energy efficient memory structure," in MICRO 30: Proc. of the 30th annual ACM/IEEE international symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 1997, pp. 184-193.
8. R. Krashinsky, C. Batten, M. Hampton, S. Gerding, B. Pharris, J. Casper, and K. Asanovic, "The vector-thread architecture," in ISCA '04: Proc. of the 31st annual international symposium on Computer architecture. Washington, DC, USA: IEEE Computer Society, 2004, p. 52.
9. L. H. Lee, B. Moyer, and J. Arends, "Instruction fetch energy reduction using loop caches for embedded applications with small tight loops," in ISLPED '99: Proc. of the 1999 international symposium on Low power electronics and design. New York, NY, USA: ACM, 1999, pp. 267-269.
10. Y. Mathys and A. Châtelain, "Verification strategy for integration 3G baseband SoC," in DAC '03: Proc. of the 40th conference on Design automation. New York, NY, USA: ACM Press, 2003, pp. 7-10.
11. J. H. Moreno et al., "An innovative low-power high-performance programmable signal processor for digital communications," IBM J. Res. Dev., vol. 47, no. 2-3, pp. 299-326, 2003.
12. S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. López-Lagunas, P. R. Mattson, and J. D. Owens, "A bandwidth-efficient architecture for media processing," in MICRO 31: Proc. of the 31st annual ACM/IEEE international symposium on Microarchitecture. Los Alamitos, CA, USA: IEEE Computer Society Press, 1998, pp. 3-13.
13. S. Rixner, W. J. Dally, B. Khailany, P. R. Mattson, U. J. Kapasi, and J. D. Owens, "Register organization for media processing," in HPCA 6: Proc. of the Sixth International Symposium on High-Performance Computer Architecture., 2000, pp. 375-386.
14. O. Silven and K. Jyrkkä, "Observations on power-efficiency trends in mobile communication devices," EURASIP Journal of Embedded Systems, vol. 2007, no. 1, pp. 17-17, 2007.
15. M. B. Taylor, et al., "Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams," in ISCA '04: Proc. of the 31st annual international symposium on Computer architecture. Washington, DC, USA: IEEE Computer Society, 2004, p. 2.
16. J. Zalamea, J. Llosa, E. Ayguadé, and M. Valero, "Two-level hierarchical register file organization for VLIW processors," in MICRO 33: Proc. of the 33rd annual ACM/IEEE international symposium on Microarchitecture. New York, NY, USA: ACM Press, 2000, pp. 137-146.