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Volumn , Issue , 2004, Pages 686-691

Heterogeneous MP-SoC - The solution to energy-efficient signal processing

Author keywords

Design Space Exploration; Energy Efficiency; MP SoC; Network on Chip; Signal Processing

Indexed keywords

MULTIPROCESSOR SYSTEMS-ON-CHIPS (MPSOC0; NETWORK-ON-CHIP; SPACE EXPLORATION;

EID: 4444353560     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (38)
  • 8
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    • Property based verification for SoC
    • November Invited Talk
    • B. Bailey. Property Based Verification for SoC. Int. Symp. on System-on-Chip (SoC), November 2003. Invited Talk.
    • (2003) Int. Symp. on System-on-Chip (SoC)
    • Bailey, B.1
  • 11
    • 4444268367 scopus 로고    scopus 로고
    • ConvergenSC. CoWare, http://www.coware.com.
    • CoWare
  • 18
    • 78650054976 scopus 로고    scopus 로고
    • Abstract RTOS modelling for multiprocessor system-on-chip
    • IEEE, nov
    • M. G. J. Madsen, K. Virk. Abstract RTOS modelling for multiprocessor system-on-chip. In International Symposium on System-on-Chip, pages 147-150. IEEE, nov 2003.
    • (2003) International Symposium on System-on-Chip , pp. 147-150
    • Madsen, M.G.J.1    Virk, K.2
  • 21
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • January
    • L. Benini, G. De Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer, pages 70-78, January 2002.
    • (2002) IEEE Computer , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 27
    • 4444312414 scopus 로고    scopus 로고
    • Open Core Protocol International Partnership (OCP-IP). OCP datasheet, http://www.ocpip.org.
    • OCP Datasheet
  • 31
    • 4444308318 scopus 로고    scopus 로고
    • SystemC initiative. http://www.systemc.org.
  • 35
    • 4444268368 scopus 로고    scopus 로고
    • A modular simulation framework for architectural exploration of on-chip interconnection networks
    • October
    • T. Kogel, M. Doerper, A. Wieferink, R. Leupers, G. Ascheid, H. Meyr, and S. Goossens. A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks. In CODES+ISSS, October 2003.
    • (2003) CODES+ISSS
    • Kogel, T.1    Doerper, M.2    Wieferink, A.3    Leupers, R.4    Ascheid, G.5    Meyr, H.6    Goossens, S.7
  • 37
    • 4444240716 scopus 로고    scopus 로고
    • Tensilica. http://www.tensilica.com.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.