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Volumn , Issue , 2004, Pages 608-613
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Automatic generation of equivalent architecture model from functional specification
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Author keywords
Formal verification; Model Refinement; System level design
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Indexed keywords
ALGORITHMS;
AUTOMATION;
COMPUTATIONAL COMPLEXITY;
COMPUTER ARCHITECTURE;
COMPUTER PROGRAMMING LANGUAGES;
VLSI CIRCUITS;
FORMAL VERIFICATION;
MODEL REFINEMENT;
SYSTEM LEVEL DESIGN;
SYSTEM LEVEL DESIGN LANGUAGES (SLDL);
SYSTEMS ANALYSIS;
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EID: 4444342512
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/996566.996732 Document Type: Conference Paper |
Times cited : (7)
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References (10)
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