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Volumn , Issue , 2004, Pages 608-613

Automatic generation of equivalent architecture model from functional specification

Author keywords

Formal verification; Model Refinement; System level design

Indexed keywords

ALGORITHMS; AUTOMATION; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; VLSI CIRCUITS;

EID: 4444342512     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996732     Document Type: Conference Paper
Times cited : (7)

References (10)
  • 1
    • 84862411082 scopus 로고    scopus 로고
    • [online]
    • SystemC, OSCI[online]. Available: http://www.systemc.org/.
  • 2
    • 4444344948 scopus 로고    scopus 로고
    • System debugging and verification: A new challenge
    • University of California, Irvine, October
    • S. Abdi and D. Gajski. System Debugging and Verification: A New Challenge. Technical Report ICS-TR-03-31, University of California, Irvine, October 2003.
    • (2003) Technical Report , vol.ICS-TR-03-31
    • Abdi, S.1    Gajski, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.