A packing algorithm for non-Manhattan hexagon/triangle placement design by using an adaptive O-tree representation

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 646-651

  Li, Jing ^a   Yan, Tan ^a   Yang, Bo ^a   Yu, Juebang ^a   Li, Chunhui ^b  

^a UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b 555 River Oaks Parkway ^*  (United States)

Author keywords

Diagonal wiring; Non Manhattan layout; O tree representation; Placement; VLSI circuit physical design; Y architecture

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MICROELECTROMECHANICAL DEVICES; OPTIMIZATION; TREES (MATHEMATICS);

DIAGONAL WIRING; NON-MANHATTAN LAYOUT; O-TREE REPRESENTATIONS; PHYSICAL DESIGNS; PLACEMENTS; Y-ARCHITECTURE;

VLSI CIRCUITS;

EID: 4444319096     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996743     Document Type: Conference Paper

References (9)

1. C. Chiang, M Sarrafzadeh, Wirability of Knock-Knee layouts with 45° wires, IEEE Trans on CAS, Vol.38, No. 6, pp. 613-624, 1991
2. Cheng-Kok Koh, Patrick H. Madden, Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures, Proceedings of the tenth Great Lakes Symposium on VLSI, pp. 47-52, March 2000
3. Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald Graham, A Hierarchical Three-way Interconnect Architecture for Hexagonal Processors, Proceedings of the 2003 International Workshop on System-level Interconnect Prediction, pp.133-139, April 2003
4. G. H. Lin G.L. Xue D.F. Zhou, Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees, International Conference on Computer Design (ICCD '99), pp. 392 -398,10-13 October 1999
5. G. H. Lin G.L. Xue, Optimal Layout of Hexagonal Minimum Spanning Trees in Linear Time, ISCAS 2000-IEEE International Symposium on Circuits and Systems, pp. IV633-IV636, May 2000
6. Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng, The Y-architecture: Yet Another On-chip Interconnect Solution, IEEE Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific, pp. 840-846, 21-24 January 2003
7. th ACM/IEEE design Automat- ion Conf., pp.268-273, June 1999.
8. Steven L. Teig, The X Architecture: Not Your Father's Diagonal Wiring , Proceedings of the 2002 International Workshop on System-level Interconnect Prediction, pp. 33 - 37, April 2002
9. http://www.cbl.ncsu.edu/