An active analog delay and the delay reference loop

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2004, Pages 17-20

  Buckwalter, James ^a   Hajimiri, Ali ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analog delay; Delay locked loop; Delay reference loop; Equalization; Tapped delay lines; True time delay

Indexed keywords

ANALOG DELAY; DELAY LOCKED LOOP; DELAY REFERENCE LOOP; TAPPED-DELAY LINES; TRUE TIME DELAY;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; EQUALIZERS; MAPPING; OPTICAL FIBERS; SIGNAL PROCESSING; TEMPERATURE DISTRIBUTION; TRANSCEIVERS; TRANSISTORS;

DELAY CIRCUITS;

EID: 4444238564     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Winters and R. D. Gitlin, "Electrical Signal Processing Techniques in Long-Haul Fiber-Optic Systems," IEEE Trans. on Communications., vol. 38, no.9, pp.1439-1453, Sept. 1990.
2. H. Wu, et al., "Differential 4-tap and 7-tap Transverse Filters in SiGe for 10 Gb/s Multimode Fiber Optic Link Equalization," ISSCC Digest of Technical Papers, pp. 180-181, Feb. 2003.
3. K. Azadet, E. F. Haratsch, H. Kim, F. Saibi, J. H. Saunders M. Shaffer, L. Song, and M.-L. Yu, "Equalization and FEC Techniques for Optical Transceivers," IEEE J. Solid-State Circuits, vo. 37, no. 3, pp.317-327, March 2002.
4. T. H. Lee and J. F. Bulzachelli, "A 155-MHz Clock Recovery Delay- and Phase- Locked Loop," IEEE J. Solid-State Circuits, vol. 27, no.12, pp.1736-1746, Dec. 1992.