Design of a micro-UART for SoC application

Computers and Electrical Engineering

Volumn 30, Issue 4, 2004, Pages 257-268

  Ali, Liakot ^a   Sidek, Roslina ^a   Aris, Ishak ^a   Mohd Ali, Alauddin ^b   Suparjo, Bambang Sunaryo ^a  

^a UNIVERSITY PUTRA MALAYSIA   (Malaysia)

^b UNIVERSITI KEBANGSAAN MALAYSIA   (Malaysia)

Author keywords

FPGA; HDL; Serial communication; SoC; UART

Indexed keywords

SERIAL COMMUNICATION; SOC; UART; UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER;

COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SCIENCE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; INTELLECTUAL PROPERTY; MARKETING; SIGNAL RECEIVERS; TRANSMITTERS;

ELECTRICAL ENGINEERING;

EID: 4444237493     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2003.01.002     Document Type: Article

References (12)

1. Altera Data book. 1998;Altera Corporation, San Jose, USA.
2. Anom, 2002. http://www.semiconductors.philips.com/news/publications/content/file_464.html.
3. Bhasker J. A Verilog HDL primer. 1998;Star Galaxy, London, UK.
4. Mano M.M. Digital design. 2002;Prentice-Hall International Inc. New Jersey, USA.
5. Lee J.M. Verilog quickstart. 1999;Kluwer Academic Publisher, Boston, USA.
6. Nelson V.P., Nagle H.T., Irwin J.D. Digital logic circuit analysis. 1995;Prentice-Hall International Inc. New Jersey, USA.
7. NSC (National Semiconductor), PC16550D, Universal Asynchronous Receiver/Transmitter with FIFOs. Datasheets, 1995.
8. O'Neill B.C., Clark S., Wong K.L. Serial communication circuit with optimized skew characteristics. IEEE Communications Letters. 5(6):2001;260-262.
9. Thomas D.E., Moorby P.R. The Verilog hardware description language. 1995;Kluwer Academic Publisher, Boston, USA.
10. Wakerly J.F. Digital design. 2000;Prentice-Hall International Inc. New Jersey, USA.
11. Yeandel J, Thulborn D, Jones S. An on-line testable UART implemented using IFIS. In: Proceedings of 15th IEEE VLSI Test Symposium, 1997. p. 344-9.
12. Yunshan Z, Marshall T. Design verification using formal techniques. In: IEEE Proceedings of 4th International Conference on ASIC, 2001. p. 21-8.