On-chip high-Q Cu inductors embedded in wafer-level chip-scale package for silicon RF application

IEEE MTT-S International Microwave Symposium Digest

Volumn 1, Issue , 2004, Pages 197-200

  Itoi, Kazuhisa ^a   Sato, Masakazu ^a   Abe, Hiroshi ^a   Sugawara, Hirotaka ^b   Ito, Hiroyuki ^b   Okada, Kenichi ^b   Masu, Kazuya ^b   Ito, Tatsuya ^a  

^a FUJIKURA LTD   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Coils; Inductors; Passive circuits; Q factor; Wafer scale integration

Indexed keywords

OPTIMUM ROUTING PATTERN; SPIRAL INDUCTORS;

COMPUTER SIMULATION; ELECTRIC COILS; ENERGY UTILIZATION; FABRICATION; INDUCTANCE; MICROPROCESSOR CHIPS; PASSIVE NETWORKS; SILICON WAFERS; THERMODYNAMIC STABILITY;

ELECTRIC INDUCTORS;

EID: 4444225321     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Yoon, B. Kim, C. Han, E. Yoon and C. Kim, "Surface Micromachined Solenoid On-Si and On-Glass Inductors for RF Applications," IEEE Electron Device Letters., vol. 20, no 9, pp. 487-489, September 1999.
2. S. Lee, S. Shin and G. Ihm, "Measured Results on Symmetric Dual-Level Spiral Inductors for RF ICs," IEICE Trans. Electron., vol. E84-C, no 6, pp. 845-848, November 2001.
3. Y. Sugimoto and S. Satoh, "A Study to Determine an Effective Ground-Shield Structure for a Silicon On-Chip Spiral Inductor," Journal of Jpn. Institute of Electronics Packaging., vol. 6, no 6, pp. 473-480, September 2003.
4. N. Sadakata, "Wafer Scale Chip Scale Package by Metal Covered Resin Core Process," SEMI Technology Symposium 2000., pp. 123-127, December 2000.
5. S. A. Wartenberg, RF Measurements of Die and Packages, Boston: Artech House, 2002.