A FPGA coprocessor for the cryptographic tate pairing over Fp

Proceedings - International Conference on Information Technology: New Generations, ITNG 2008

Volumn , Issue , 2008, Pages 112-119

  Barenghi, Alessandro ^a   Bertoni, Guido ^b   Breveglieri, Luca ^a   Pelosi, Gerardo ^c  

^a POLITECNICO DI MILANO   (Italy)

^b STMICROELECTRONICS   (Italy)

^c UNIVERSITY OF BERGAMO   (Italy)

Author keywords

FPGA; Hardware accelerator; Identity based cryptography; Tate pairing

Indexed keywords

HARDWARE ACCELERATORS; IDENTITY-BASED CRYPTOGRAPHY; TATE PAIRING;

COMPUTER HARDWARE; ENGINEERING RESEARCH; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NETWORK PROTOCOLS; PARALLEL PROCESSING SYSTEMS;

CRYPTOGRAPHY;

EID: 44049091907     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITNG.2008.260     Document Type: Conference Paper

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