Wave pipelining using self reset logic

VLSI Design

Volumn 2008, Issue , 2008, Pages

  Litvin, Miguel E ^a   Mourad, Samiha ^a  

^a Santa Clara University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; GATE DIELECTRICS; LOGIC CIRCUITS; PARAMETER ESTIMATION;

SUPPLY VOLTAGE; TEMPERATURE VARIATIONS; WAVE PIPELINING;

CMOS INTEGRATED CIRCUITS;

EID: 43949131048     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/2008/738983     Document Type: Article

References (6)

1. Litvin M. E., Wave pipelining with self reset logic, Doctoral dissertation
2. Litvin M. E., Mourad S., Self reset logic for fast arithmetic applications IEEE Transactions on Very Large Scale Integration Systems 2005 13 4 462 475
3. Litvin M. E., Mourad S., Wave pipelining with self reset logic Proceedings of IEEE International Conference on Electronic Circuits Systems (ICECS 06) December 2006 Nice, France
4. Klass E. F., Wave pipelining theoretical practical issues in CMOS, Doctoral dissertation
5. Lam W. K. C., Brayton R. K., Sangiovanni-Vincentelli A., Valid clocking in wavepipelined circuits Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD 92) November 1992 Santa Clara, Calif, USA 518 525
6. Wentai L., Gray C. T., Fan D., Farlow W. J., Hughes T. A., Cavin R. K., 250-MHz wave pipelined adder in 2- m CMOS IEEE Journal of Solid-State Circuits 1994 29 9 1117 1128