Compiler control power saving scheme for multi core processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4339 LNCS, Issue , 2006, Pages 362-376

  Shirako, Jun ^a   Oshiyama, Naoto ^a   Wada, Yasutaka ^a   Shikano, Hiroaki ^a   Kimura, Keiji ^a   Kasahara, Hironori ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY CONSERVATION; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS;

MULTI CORE PROCESSORS; PARALLELIZE PROGRAM;

PROGRAM COMPILERS;

EID: 43949122214     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-69330-7_25     Document Type: Conference Paper

References (19)

1. M.Wolfe. High performance compilers for parallel computing. Addison-Wesley Publishing Company, 1996.
2. R. Eigenmann, J. Hoeflinger, and D. Padua. On the automatic parallelization of the perfect benchmarks. IEEE Trans, on parallel and distributed systems, 9(1), Jan. 1998.
3. M. W. Hall, J. M. Anderson, S. P. Amarasinghe, B. R. Murphy, S. Liao, E. Bugnion, and M. S. Lam. Maximizing multiprocessor performance with the suif compiler. IEEE Computer, 1996.
4. Marc Gonzalez, Xavier Martorell, Jose Oliver, Eduard Ayguade, and Jesus Labarta. Code generation and run-time support for multi-level parallelism exploitation. In Proc. of the 8th International Workshop on Compilers for Parallel Computing, Jan. 2000.
5. H. Honda, M. Iwata, and H. Kasahara. Coarse grain parallelism detection scheme of a fortran program. Trans. of IEICE, J73-D-l(12):951-960, Dec. 1990.
6. H. Kasahara et al. A multi-grain parallelizing compilation scheme on oscar. Proc. 4th Workshop on Language and Compilers for Parallel Computing, 1991.
7. Hironori Kasahara. Advanced automatic parallelizing compiler technology. IPSJ MAGANIE, Apr 2003.
8. David H. Albonesi et al. Dynamically tuning processor resources with adaptive processing. In IEEE Computer, Dec. 2003.
9. Q. Wu, P. Juang, M. Martonosi, and D. W. Clark. Formal online methods for voltage/frequency control in multiple clock domain microprocessors. In Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2004.
10. Chung-Hsing Hsu and Ulrich Kremer. The design, implementation, and evaluation of a compiler algorithm for cpu energy reduction. In The ACM SIGPLAN Conference on Programming Language Design and Implementation, Jun. 2003.
11. M. Obata, J. Shirako, H. Kaminaga, K. Ishizaka, and H. Kasahara. Hierarchical parallelism control for multigrain parallel processing. In Proc. of 15th International Workshop on Languages and Compilers for Parallel Computing, Aug. 2002.
12. K. Ishizaka, T. Miyamoto, M. obata J. Shirako, K. kimura, and H. Kasahara. Performance of oscar multigrain parallelizing compiler on smp servers. In Proc. of 17th International Workshop on Languages and Compilers for Parallel Computing, Sep. 2004.
13. Jun shirako, Kouhei Nagasawa, Kazuhisa Ishizaka, Motoki Obata, and Hironori Kasahara. Selective inline expansion for improvement of multi grain parallelism. PDCN2004, Feb. 2004.
14. H. Kasahara, H. Honda, M. Iwata, and M. Hirota. A compilation scheme for macro-dataflow computation on hierarchical multiprocessor system. Proc. Int Conf. on Parallel Processing, 1990.
15. H. Kasahara, S. Narita, and S. Hashimoto. Architecture of oscar. Trans of IEICE, J71-D(8), Aug. 1988.
16. H. Kasahara, H. Honda, and S. Narita. Parallel processing of near fine grain tasks using static scheduling on oscar. Proceedings of Supercomputing '90, Nov. 1990.
17. K. Kimura, W. Ogata, M. Okamoto, and H. Kasahara. Near fine grain parallel processing on single chip multiprocessors. Trans. of IPSJ, 40(5), May. 1999.
18. David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. of the 27th ISCA, Jun. 2000.
19. Hiroshi Kawaguchi, Youngsoo Shin, and Takayasu Sakurai. uitron-lp: Power-conscious real-time os based on cooperative voltage scaling for multimedia applications. In IEEE Transactions on multimedia, Feb. 2005.