New test structure to monitor contact-to-poly leakage in sub-90 nm CMOS technologies

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 2, 2008, Pages 244-247

  King, Ming Chu ^b   Chin, Albert ^a,b  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Contact; Gate; Leakage current; Test structure

Indexed keywords

GATE DIELECTRICS; LEAKAGE CURRENTS; NANOTECHNOLOGY; PROBLEM SOLVING;

GATE ELECTRODES; TEST STRUCTURES;

CMOS INTEGRATED CIRCUITS;

EID: 43849105261     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2008.2000267     Document Type: Conference Paper

References (11)

1. G. Freeman, W. Lukaszek, T. W. Ekstedt, and D. W. Peters, "Experimental verification of a novel electrical test structure for measuring contact size," IEEE Trans. Semiconduct. Manuf., vol. 2, pp. 9-15, Feb. 1989.
2. R. A. Ashton, B. C. Kane, J. W. Blatchford, and D. M. Shuttleworth, "Test structures for evaluating strong phase shift lithography," IEEE Trans. Semiconduct. Manuf., vol. 15, pp. 195-200, May 2002.
3. C. B. Sia, B. H. Ong, K. M. Lim, K. S. Yeo, M. A. Do, J. G. Ma, and T. Alam, "A novel RFCMOS process monitoring test structure," in Proc. Int. Conf. Microelectronic Test Structures, Mar. 2004, pp. 45-50.
4. H. Terletzki and L. Risch, "Electrostatic discharge test structures for CMOS circuits," in Proc. IEEE 1989 Int. Conf. Microelectronic Test Structures, Mar. 1989, vol. 2, pp. 255-261.
5. S. Ido, M. Imai, T. Kumise, M. Satoh, H. Horie, and S. Ando, 'The vertical test structure for measuring contact resistance between two kinds of metal," in Proc. IEEE 1991 Int. Conf. Microelectronic Test Structures, Mar. 1991, vol. 4, pp. 29-34.
6. H. Y. Li, W. H. Li, L. Y. Wong, and N. Hwang, "Built-in via module test structure for backend interconnection in-line process monitor," in Proc. 12th IPFA 2005, Singapore, pp. 167-170.
7. A. Cabrini, D. Cantarelli, P. Cappelletti, R. Casiraghi, A. Maurelli, M. Pasotti, P. L. Rolandi, and G. Torelli, "A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies," IEEE Trans. Semiconduct. Manuf., vol. 19, pp. 57-66, Feb. 2006.
8. C. Hess, B. E. Stine, L. H. Weiland, T. Mitchell, M. P. Karnett, and K. Gardner, "Passive multiplexer test structure for fast and accurate contact and via fail-rate evaluation," IEEE Trans. Semiconduct. Manuf., vol. 16, pp. 259-265, May 2003.
9. K. N. Chen, A. Fan, C. S. Tan, and R. Reif, "Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology," IEEE Electron Device Lett., vol. 25, pp. 10-12, Jan. 2004.
10. J. Santander, M. Lozando, A. Collado, M. Ullan, and E. Cabruja, "Accurate contact resistivity extraction on Kelvin structures with upper and lower resistive layers," IEEE Trans. Electron Devices, vol. 47, pp. 1431-1439, Jul. 2000.
11. Y. Hamamura, T. Kumazawa, K. Tsunokuni, A. Sugimoto, and H. Asakura, "An advanced defect-monitoring test structure for electrical screening and defect localization," IEEE Trans. Semiconduct. Manuf., vol. 17, pp. 104-110, May 2004.