Performance constraints aware voltage Islands generation in SoC floorplan design

2006 IEEE International Systems-on-Chip Conference, SOC

Volumn , Issue , 2006, Pages 211-214

  Lu, Ming Ching ^a   Wu, Meng Chen ^b   Chen, Hung Ming ^b   Jiang, Hui Ru ^b  

^a SpringSoft Inc   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTELLECTUAL PROPERTY; LOGIC DESIGN; OPTIMIZATION; QUALITY MANAGEMENT;

PERFORMANCE CONSTRAINTS; SYSTEM-ON-A-CHIP (SOC) DESIGNS; VOLTAGE ISLANDS;

MICROPROCESSOR CHIPS;

EID: 43749116417     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2006.283883     Document Type: Conference Paper

References (13)