Scalable architecture for word HMM-based speech recognition

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2004, Pages

  Yoshizawa, Shingo ^a   Wada, Naoya ^a   Hayasaka, Noboru ^a   Miyanaga, Yoshikazu ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MATHEMATICAL MODELS; REAL TIME SYSTEMS; VECTOR QUANTIZATION;

REAL-TIME RESPONSE; SCALABLE ARCHITECTURE; SPEECH FEATURE VECTORS; SYSTEM RECOGNIZERS;

SPEECH RECOGNITION;

EID: 4344714150     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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